Split Cache Modification for the ZipGSX DISCLAIMER: Any modifications made to the ZipGSX product that deface, damage, or alter the product may invalidate any existing warranty. Zip Technologies may deny warranty coverage for any product received with modifications made outside the direction of Zip Technologies. In this case, nominal services charges would apply for whatever services are required. What Is A "Split Cache"? The processor makes accesses to memory that are for either the executing program code or the data being accessed by the code. Some of the accesses from the processor are for the program code that is running. The other accesses are for the data being used by the executing program. In a normal cache memory archetecture, both the program code and the data are treated with no distinction. Both code and data reside within the cache memory array and are thus both accellerated. A split cache simply divides the cache memory into two separate sections reserving one for the program code, and the other for the data accessed by the code. The program code will reside in one reserved section of the cache memory. The data will reside in a separate isolated section of the cache memory. Depending on the application type, this can cause a marked increase in the performance of the cache memory. On the other hand, a degradation of performance can occur for some applications inhibited by the reduced cache size for the program code or the data. How Does a Split Cache Help Performance? As an example, in a 16K cache system, there is 16K of memory which can be used freely for code or data. There are no restrictions besides the total amount of memory available. The cache can hold up to 16K of data or up to 16K of program code, or any combination of the two adding up to 16K. If a program is moving a large data block, the program code executing may be displaced by the data that is being moved. When this happens, the program code must be reloaded into the cache memory and will cause performance to diminish. By splitting the 16K cache, there are two separate 8K cache sections. One section is only for code and the other is only for data. The effective size of the cache memory is reduced to 8K, even though the total amount of cache memory remains at 16K. By separating the two sections in this way, program code can be isolated from large data blocks. In the case of the large data transfer described above, the program code is not displaced by the data since the data activity is occuring in a physically separate section of the cache memory from the program code section. In this case, regardless of the size of the data being moved, the program code can be cached since it is not displaced by the data thus increasing the overall speed of the data transfer. How does a Split Cache Reduce Performance? Splitting of the cache reduces both the amount of data and the amount of program code that can be cached at any one time by one half. If a certain part of the program code cache memory is not required, it cannot be used for data. Likewise is the case for any unneeded data cache memory. By restricting the use of the cache memory in this way, a program executing must be able to run efficiently out of half the cache memory. Generally, the reduction of the amount of cache available for program code will cause any program to run slower. It is not always true that, for a particular application, the reduced speed due to the reduction of cache size is offset by the increased speed derived by isolating the data. Additionally, any data written by the processor may be used later for either program code or data. As data is read by the processor, certain information is supplied that can be used to determine whether the processor is reading program code or data. A split cache system will update the appropriate section of the cache. Data being written, however, has no such information and therefore a split cache system does not know in which section to place the data. This special condition requires the split cache system to simultaneously update both the data and program code cache memories. This effectively eliminates some of the advantages that the split cache provides by unnecessarily displacing some program code with data (or potentially some data with program code). Which System Is Right For Me? The decision to use one method or another depends on the application being performed. Experimentation and timing of applications in both configurations would reveal the best for an individual. Who Can Make A Split Cache Modification? Modifying a ZipGSX for a split cache is quite simple if you can use a soldering iron and a knife. The ZipGSX accelerator was designed to make this easy. The only restrictions are that you have a ZipGSX Version 1.02 accellerator with either 16K or 64K of cache. To modify a ZipGSX with 8K or 32K of cache, you must first upgrade your cache to either 16K or 64K. How To Make The Modification To modify the cache configuration for a split cache, you must have a ZipGSX accelerator board version 1.02. You must also have either 16K of cache, or 64K of cache. Neither the 8K nor the 32K configurations may be split. 1. Remove the gray cable at J1. 2. Locate J6 and J7 which can be found just between J1 and U9 at the bottom of the card. 3. Cut and remove the small trace between pin 2 and pin 3 of both J6 and J7. The actual trace connection is on the reverse side of the card. 4. Solder a small piece of wire between pin 1 and pin 3 of both J6 and J7. 5. If you are starting with a 64K cache system that you are trying to split, skip to step #9. Otherwise continue with step 6. 6. Locate J8 which is just below the second cache memory chip labeled U4. 7. Cut and remove the small trace between pin 1 and pin 2 of J8. 8. Solder a small wire between pin 2 and pin 3 of J8. 9. Locate SW1, the top dip switch block. On SW1, locate the bottom two switches numbered 7 and 8. 10. Set switch 8 to the ON position. 11. Switch 7 must be set depending on the original amount of memory. If you are converting a 64K cache, set switch 7 to the OFF position - you now have a "split" 32K system. If you are converting a 16K cache, set switch 7 to the ON position - you now have a "split" 8K system.