Subject: Re: 6502 assembler Newsgroups: comp.sys.apple2.programmer From: dempson@actrix.gen.nz (David Empson) Date: Wed, 29 Sep 1999 01:43:27 +1200 Message-ID: <1dyvc4q.1hrmrbg68993gN@dempson.actrix.gen.nz> References: <4iVF3.2276$QJ.87287@typ11.nn.bcandid.com> <7sc1ps$c8l$1@news.rt66.com> <37ED98A4.8E434651@plano.net> <7sot34$2db$1@nnrp1.deja.com> Organization: Empsoft User-Agent: MacSOUP/2.4 NNTP-Posting-Host: 202.49.157.176 X-Original-NNTP-Posting-Host: 202.49.157.176 X-Trace: 29 Sep 1999 01:41:54 NZST, 202.49.157.176 Lines: 120 Path: lobby!newstf02.news.aol.com!portc02.blue.aol.com!howland.erols.net!newsfeed.direct.ca!usenet.net.nz!news.iprolink.co.nz!news.actrix.gen.nz!dempson Pardon the corrections. I'm in a pedantic mood this evening. :-) Date Doctor - the best y2k fix wrote: > there is also INA, DEA, but they are undocumented and only on the newer > //e's - the ones with mouse characters I believe. They aren't "undocumented". They are documented completely in anything which covers the 65C02 processor. The 65C02 (as used in the IIc and enhanced IIe) adds about 26 new opcodes. Some of these are outright new instructions (TRB/TSB), others are new addressing modes (INC A, DEC A; aliased as INA and DEA). > the addressing modes are eg. STA $00 or STA ($00) or STA $0000 or STA > ($0000) or STA $0000,x or STA ($0000,x) or maybe even STA ($0000),x (x > or y in each case, examples are zero page, indirect zp, 16-bit, indirect > 16-bit, 16bit with offset, indirect with offset, Some of those don't exist (for the STA instruction, anyway). Here is a full list of the addressing modes for the LDA instruction, for the 6502. These all apply to LDA, STA, ADC, SBC, AND, ORA, XOR and CMP, with one exception: there is no STA immediate. :-) LDA #$nn Immediate LDA $nn Zero page LDA $nnnn Absolute LDA $nn,X Zero page indexed with X [Note: X only] LDA $nnnn,X Absolute indexed with X LDA $nnnn,Y Absolute indexed with Y LDA ($nn,X) Zero page indexed indirect [Note: X only] LDA ($nn),Y Zero page indirect indexed [Note: Y only] The 65C02 adds one addressing mode: LDA ($00) Zero page indirect The 65816 adds six addressing modes: LDA $nnnnnn Absolute long LDA $nnnnnn,X Absolute long indexed with X [Note: X only] LDA [$nn] Direct indirect long LDA [$nn],Y Direct indirect indexed long LDA $nn,S Stack relative LDA ($nn,S),Y Stack relative indirect indexed ("Direct" is equivalent to "zero page" for the earlier processors. The 65816 has a D register which sets the base address of the direct page anywhere in the first 64K bank.) The 65816 immediate mode can be either 8-bit or 16-bit depending on a flag setting. Some other instructions have additional special addressing modes. Some examples: LDX $nn,Y Zero page indexed with Y JMP ($nnnn) Absolute indirect JMP ($nnnn,X) Absolute indexed indirect (65C02 and 65816 only) > then there is PHA, PHP, PLA, PLP, for pushing accumulator or program > counter onto the stack. PHP/PLP deal with the processor flags. There is no way to directly push or pull the program counter, except in a slightly modified form with the JSR, RTS and RTI instructions (or with an interrupt). > then BNE, BEQ, BLT, BGT, BGE, BLE, BCS, --- branch if not eq, eq, less > than, grt, g or eq, less or eq, carry set, BZS (zero flag set), BMI > (minus), BPL (plus - < 128) Several of those don't exist. The set of branches are: BNE Branch if not equal BEQ Branch if equal BPL Branch if plus BMI Branch if minus BCC Branch if carry clear BCS Branch if carry set BVC Branch if overflow clear BVS Branch if overflow set The 65C02 adds BRA (branch always), and the 65816 adds BRL (branch long). There are aliases for some of these instructions: BLT Branch if less than (same as BCC) BGE Branch if greater than or equal (same as BCS) There is no single instruction to do a "branch if less than or equal", or a "branch if greater than". These can be synthesised with two consecutive branch instructions. Similarly there are no signed branch instructions. > then theres some instruction to move the flags to a register - maybe you > PHF then PLA or something, then you can do bit operations PHP, PLA. > AND, ORA, XOR respectively. EOR, actually. (Some assemblers accept XOR as an alias.) > also, most of the ADD ADC, SUB, SBC, and bitwise all have zero page and > 16-bit at least for addressing modes. The 6502, 65C02 and 65816 do not have an ADD or SUB instruction. You must always add or subtract with carry. > (BZS - branch if zero flag set) Never seen this one. BEQ is the correct name. -- David Empson dempson@actrix.gen.nz Snail mail: P O Box 27-103, Wellington, New Zealand