Csa2 FAQs-on-Ground file: Csa2ACCEL.txt rev013 3/28/1999
Home is Main Hall-1 FAQs Contents is Main Hall-2
The Csa2 (comp.sys.apple2) Usenet newsgroup Frequently Asked
Questions files are compiled by the Ground
Apple II site,
1997 - 1999.
____________________________
001- What are the correct settings for a ZipGS?
002- Why should Appletalk Delay be disabled
with a ZipGS?
003- How do I set up a Transwarp on my IIe?
004- Is there a way of disabling Transwarp
for games?
005- What are specs & jumper settings
for a vintage SpeeDemon?
006- How does the SpeeDemon rate as an accelerator?
007- My SpeeDemon accelerator board seems
to run hot. A fix?
008- How should the DIP switches be set on
a v3.03 SpeeDemon?
009- How can I get a 'Cache Hit' indicator
for my ZipGS?
010- How can I program the ZipGS registers?
011- How can I set up a ProDOS sys file to
turn my ZipGS OFF/ON?
012- Is there some ZipGS mod that will improve
performance?
013- I have a 7MHz ZipGS. How fast can the
board be pushed?
014- What Oscillator freq corresponds to what
upgrade speed?
015- How do I experiment with different oscillator
frequencies?
016- How do I modify my ZipGS to accept the
new "skinny" RAM chips?
017- Is it really necessary to increase board
voltage
018- What kind of performance increase can
I expect?
019- How can I modify my ZipGS for more cache
and more speed?
020- Do I need new GALs to speed up my TransWarpGS?
021- How does a TWGS cache upgrade compare
with a speed upgrade?
022- How can I upgrade my TWGS to 32k cache?
023- How can I upgrade TWGS speed?
024- What kind of RAMs do I need for a TWGS
or ZipGS speedup?
025- How can I tell the firmware version of
my TWGS?
026- For my TWGS, do I need the 2B GAL to
use a SCSI interface card?
027- Why are my ZipGS settings via the Zip
CDA forgotten?
028- What do the check-marks mean in the ZipGS
CDA?
029- Why don't my ZipGS settings match DIP
switch settings!?
030- I have a ZipGS. Sometimes my GS 'hangs'
on power-up. Why?
031- The speedup has led to system crashes.
What's the problem?
032- A new accelerator board has led to crashes.
What's the problem?
001- What are the correct settings for a ZipGSx? I've tinkered
with "CPS Follow", "Counter Delay"
and the like but have
no idea what I'm actually doing.
CPS Follow should always be enabled. If you disable it you will
have problems
with Disk ]['s and System 6's AppleTalk driver and anything else
that expects
the Zip to slow down to 1 mhz when the GS is instructed to slow
down to 1mhz.
For instance, border text demos (like the FTA XMAS demo) won't
work if you have
this disabled. Expect weird things to happen if you play with this
one.
Counter Delay I would recommend leaving enabled. This causes the
Zip to
"deaccelerate" (actually all it does is temporarily ignore that
any data can be
read from the cache instead of the motherboard) for about 5 milliseconds
any
time you read one of the Video Counters -- this is really only
there so that
one of the self-tests will pass. Which way you set it shouldn't
be fatal.
AppleTalk or Interrupt Delay should always be disabled. The desktop
will run
much slower if you enable it. The only reason most people needed
it was for
AppleTalk under system 5, and I have an init on tybalt that fixes
that. System
6 fixed the problem but requires CPS Follow to be enabled for the
fix to work.
Speaker and Paddle delays are intended to let old 1-bit sounds and
Paddle
access work the way they do on an unaccelerated IIgs. I recommend
leaving these
on unless you feel like experimenting. They shouldn't be fatal
but some program
might react very negatively, so be prepared.
Bank C/D cache enable -- leave this at the default setting and forget
about it.
This tells the Zip if it's OK to cache bank-switched RAM (the old
language card
area). Zip's own docs say "there is no know software requiring
this" but that
it why it's there, in case somebody ever finds software that doesn't
like it
you can try setting it the other way.
002- Why should Appletalk Delay be disabled with a ZipGS?
Because it saps performance every time an interrupt occurs.
The Appletalk delay was originally called the "Interrupt Delay"
but they
renamed it at the last minute because somebody actually tried an
8/64 on an
Appleshare network and it dropped packets like crazy.
With "Appletalk delay" on, every time an interrupt occurs your Zip
will disable
acceleration for 5 ms, just like it does with the paddles and the
speaker and
the others. This is a significant effect because with VBL interrupts
going you
have one every 16 ms, so your Zip spends nearly 1/3 of the time
not
accelerating you.
Why this "fixes" appletalk: in system 5 and earlier (including the
ROM
appletalk code), there are software timing loops which assume 2.8
mhz
operation. As you speed the system up, it gets more and more likely
to drop
incoming packets because it thinks they are being sent too slowly
to be
correct, when in reality the appletalk code is timing out too fast.
Why the Appletalk delay is not a complete solution: a full-size
Appletalk
packet that you'd get from a file server takes about 14 ms to transmit.
The
Appletalk delay covers the first 1/3 of the packet, the VBL interrupt
covers at
most another third of the packet, but nothing is guaranteed to
keep
acceleration off for the whole packet. If you speed the Zip up
more, say to
10/64, it starts dropping long packets no matter what.
This latter problem was why I originally wrote ZipTalk. It required
a slot
delay to be enabled (in, say, slot 6 or 7), and before each appletalk
packet
was received I tweaked that slot -- slot delays are 50 ms, so the
Zip stays
unaccelerated way past the end of the packet and everything works.
(I also
patched packet sending, to be safe.)
In system 6 Apple fixed things correctly in the appletalk drivers.
I removed
the code from ZipTalk and released what remained as ZipFix. As
of 6.0.1, the
cursor flicker problem was fixed by apple in the control panel,
so now you only
need ZipFix for the GS/OS SET_SYS_SPEED hook, which nobody seems
to use.
______________________________
003- How do I set up a Transwarp on my IIe?
Bank1: Sw 1-7 -> Change to OPEN if there is a memory card that uses
the
"Langauge Card bank switching technique". (Normally CLOSED)
Bank1: Sw 1-7 -> Change to OPEN if the plug in card must be accessed
at 1 MHz
(Normally CLOSED. OPEN for Floppy diskette controllers)
Switch 8 on both Banks: Sets the power up speed of Transwarp
Bank1 Bank2
3.6 MHz OPEN
OPEN <<Normal>>
1.7 MHz CLOSED
OPEN
1 MHz
OPEN CLOSED
1 MHz CLOSED
CLOSED
004- Is there a way of disabling Transwarp for games?
Press <Esc> at power-up will disable Transwarp completely until
the next power
off/on cycle.
A better way is to write a 01 to $C074. This will slow Transwarp
down to 1 MHz
without disabling it completely. Writing a 00 to $C074 will
restore Transwarp
to it's 'fast' speed.
005- I recently bought an "M-c-T SpeeDemon" board. It's dated
1984
and draws a small apple on the screen
after power-up. What kind
of cache RAM does it have? There's
a place for jumpers near the
top of the card. Is there a way to
control this thing through
software or hardware?
Your card may be a slightly later model.
(I've never noticed ours draw a
hires apple on the screen-- darn it!) Possibly, McT came
out with a revision
aimed at 128K IIe's.
The RAMs on our vintage model SpeeDemon
are 100ns 2048x8 9128's (for a
total 8K of pretty speedy cache).
I once asked McT about the jumper block
you mention, they said the jumper
is set at the factory to adjust on-card timing and to Leave It
Alone. (On our
card, the jumper block has 5 pairs. The pair 2nd from the top is
jumpered.)
There is also a jumper pair near the bottom
middle of the card. This is
the Speed Jumper. Jumper it if you want 'demon to slow down for
I/O accesses to
Slots 4 & 5. (The 'demon always slows for Slot 6 I/O ($C0E0
- $C0EF.)
According to the "Manual" (a folded card),
pressing PDL-1 (Closed-Apple
on a IIe) upon power-up will engage a self-test. Pressing ESC at
power-up will
turn OFF the card and allow running at normal speed. To turn OFF
the card later
on, do a POKE (49152+256*S) where S= Slot # of the slot the card
is in; then,
press RESET.
You can put the 'demon into any Slot; but,
if you put it in Slot 0 (Slot 3
in a IIe), the card will not respond to any KB shut-off commands.
006- How does the SpeeDemon rate as an accelerator
for II+
and IIe Apples?
In terms of raw performance (once you arrange
for cooling), SpeeDemon may
be the best of the 4MHz accelerators for early II's. I've never
noticed any
compatibility problems and the approx. X3.5 speed increase puts
real 'snap'
into your machine's response. (Besides, it's great for games like
Elite!)
007- My SpeeDemon accelerator board seems to
run hot in my II+.
Is this normal? Should I add cooling?
Indeed, the 'demon is a power gobbler--
roughly 1.5A as I recall-- and
some of the IC's run hot. When the board bombed after one long
session, we cut
out a square section on the back of the II+ and added a mini-fan,
just to blow
air across the 'Demon board. This ended the heat problem.
008- How should the DIP switches be set on a version 3.03
SpeeDemon board?
This is from the 1-page manual that comes with the card:
For owners without a Bank Switch Language Card
in thier Apple, the first
seven DIP switches control the access speed of the following:
switch 1
-- controls -- slot 1
switch
2 -- " -- slot 2
switch
3 -- " -- slot 3
switch
4 -- " -- paddle/joystick port
switch
5 -- " -- slot 5
switch
6 -- " -- slot 6
switch
7 -- " -- slot 7
OFF indicates slot/port is accessed at High Speed.
ON indicates slot/port is to Slow Down for access.
All slots that can be accessed at High
Speed and all empty slots should
have the corresponding Dip switch set to "OFF" (this is the non-bank
switch
setting).
Special Note about Switch 4:
Switch 4 on the SpeeDemon DIP switch no
longer controlsthe access speed to
slot 4. It now controls how the joystick and paddles are read.
If switch 4 is in the "ON" position, the
SpeeDemon will slow down to
normal Apple speed for 50 milliseconds each time the joystick is
accessed. This
allows the software to read the joystick or paddles correctly.
If switch 4 is
in the "OFF" position, the SpeeDemon will not slow down when they
are accessed.
Access to slot 4 is always at SLOW (normal) Apple speed.
Certain programs, such as Appleworks, use
the joystick location, even when
the joystick is not in use. If dip switch 4 is set to "ON"
then these programs
will not show any speed for some functions, such as calculations
and sorts.
Therefor, unless you need youysticks for your applications, switch
4 should be
set in the "OFF" position.
If you have a Bank Switch Card (extended
80-col card, Ramworks II, Titan
Saturn 128k card, excetera..) set switch 8 to the "ON" position.
Bank Switch Language Card Location:
Dip Switches 1-3 encode the location of your Bank switch
language card. Use
the following table to find the appropriate setting for your machine:
Dip Switch Bank Switch Card Location
1
2 3 Slot #
--- --- ---
------
off off off
0
off off on
1
off on
off 2
off on
on 3
on off
off 4
on off
on 5
on on
off 6
on on
on 7
If you have two bank switch cards in your system, one must reside
in slot 0.
The other must be in the slot selected by DIP switches 1-3 above.
Special Note: Because the first three switches are
used to encode the
location of the Bank Switch Language Card, you can no longer control
the speed
of all the slots. Specifically you can not control slots
1,3, or 6. These
slots woll now always run Fast except for slot 6 which will always
run Slow.
Special Note: The slot that the SpeeDemon card resides
in should be set to
the "Off" position
009- How can I get a 'Cache Hit' indicator for my ZipGSx?
This latest ZipGSx modification is pretty straightforward. When
I decided I
wanted a Cache HIT light instead of a Cache MISS light, I went
to Rat Shack and
bought a pack of Green LEDs (I like green. Blue or Orange will
work just as
well.)
I tried adding an inverter to the circuit but it just didn't want
to play
(obviously a cache HIT is the opposite of a cache MISS, and the
LED on the
board lights up for cache MISSes). Through the experimenting,
I found that I
could get the LED to light as desired without any "extra" hardware
except the
LED itself.
Simple mod: solder in the Anode of the LED to the Anode of
the Cache Miss.
Solder the Cathode to the Cathode of the Power LED.
(Even easier way to say it: there are four solder points for the
existing LEDs.
We use the two in the middle. The long lead goes to the yellow
side, the short
to the red. position as is comfortable. I can only
guess that this would be a
nice thing to attach to the TURBO light on the front of a tower
case, should
anyone ever mount a IIgs/ZipGSX inside a tower case... (also, it
might be nice
to turn SW1-6 OFF and connect the pins to the TURBO button on front.
I don't
know how useful it would be, but it might come in handy one of
these days...)
010- How can I program the ZipGSx registers?
ZipChip GS Special Registers Ex ZIP Technology, 12 October 1990
Registers must be unlocked before they can be accessed (see $C05A).
Locking
them will re-enable the annunciators.
Writing to any I/O location $C058-$C05F (whether registers are locked
or
unlocked) will reset delay in progress.
$C058 R No operation
$C058 W Write any value to force power-on/reset bit
to COLD (forces next
reset to restore ZIP registers to defaults/switch settings).
$C059 R/W 76543210
*.......
Bank Switch Lang Card cache disable=1/enable=0?
.*......
Padl delay (5 ms) disable=0/enable=1 $C070/$C020
..*.....
External delay (5 ms) disable=0/enable=1
...*....
Cntr delay (5 ms) disable=0/enable=1 $C02E/$C07E
....*...
CPS follow disable=0/enable=1
.....*..
Last Reset warm?
READ ONLY
......*.
Hardware DMA
READ ONLY
.......*
non-GS (0)/GS (1)
READ ONLY
$C05A R 76543210
****....
Current ZIP Speed, 0=100%, 1=93.75%,..., F=6.25%
....1111
$C05A W Write values as follows:
$5x
Unlock ZIP registers (must write 4 times)
$Ax
Lock ZIP registers
other
Force ZIP to follow system clock (disable card)
$C05B R 76543210
*.......
1msclk - clock with 1 ms period
.*......
cshupd - Tag data at $C05F updated
(read $C05F to reset)
..*.....
Bank Switch Language Card cache (0), don't (1)
...*....
Board disable - 0=enabled, 1=disabled
....*...
delay in effect (0=ZIP, 1=Slow)
.....*..
rombank (0/1) - not in development version
......**
Cache RAM size (00=8k, 01=16k, 10=32k, 11=64k)
$C05B W Write any value to force ZIP to current speed
(i.e. enable card)
$C05C R/W 76543210
*******.
Slot 7-1 delay enable (all slots 52-54 ms)
.......*
Speaker delay enable (5 ms)
$C05D R Current 65816 bank
$C05D W 76543210
****....
Set ZIP speed, 0=100%, 1=93.75%, ..., F=6.25%
....****
Don't care
$C05E R Read last Tag data written and force the next
write
to create
a trash tag value.
$C05E W No operation
$C05F R Read last Tag data written and reset cshupd.
Note: apparently
any write to a ZIP register
(unlocked) will
clear cshupd, but cshupd
says that
this location must be read.
$C05F W No operation
011- Is it possible to set up a simple ProDOS-8
application
(SYS) file which turns the ZipGS OFF or ON?
From the usual BASIC prompt, get into the Monitor (e.g. CALL -151)
and type in
the following code to turn OFF the ZipGS ...
2000:A9 50 8D 5A C0 8D 5A C0 8D 5A C0 8D 5A C0 8E 5A
2010:C0 0A 8D 5A C0 20 00 BF 65 1D 20 00 00 04 00 00
2020:00 00 00 00
A 2000L should look something like this ...
2000: A9 50 LDA #$50
2002: 8D 5A C0 STA $C05A ; write
$50 to $C05A four times to
2005: 8D 5A C0 STA $C05A ; enable
access to the ZIP registers
2008: 8D 5A C0 STA $C05A
200B: 8D 5A C0 STA $C05A
200E: 8E 5A C0 STZ $C05A ; write
$00 to $C05A to disable ZIP
2011: 0A ASL
= SLOW mode
2012: 8D 5A C0 STA $C05A ; write
$A0 to stop accessing ZIP
2015: 20 00 BF JSR $BF00 ; Do a ProDOS
QUIT call
2018: 65 $65
2019: 1D 20 $201D
201B: 00 00 BRK $00
201D: 04 00 00 00 00 00 00
Use the following commands to save it:
CREATE SLOW,TSYS
BSAVE SLOW,TSYS,A$2000,L$24
To enable the ZipGS (= FAST mode), simply change one byte:
200F:5B
(this changes the STZ $C05A to STZ $C05B)
CREATE FAST,TSYS
BSAVE FAST,TSYS,A$2000,L$24
Reference: FAQs resource file R005SPLITC.GIF (pic file)
012- Is there some ZipGSx mod that will improve performance
without going to a faster crystal,
etc.?
There is; you can do the ZipGSx Split Cache
Mod. As your manual explains,
Zip GSX speed comes from having a faster processor which can access
code and
data from its high-speed cache RAM. The standard 'GSX has a unified
cache,
which means data and code have the possibility of overlapping.
If the cache
controller sees a need to bring in a lot of code, it will go to
main memory and
bring in up to 64k of code (or 16k in a 16k cache system) and,
possibly,
overwrite useful data.
The reverse is also true. If the controller
feels that a lot of data needs
to be brought in, it will cache the data, and, possibly, overwrite
useful code,
causing another slowdown when the code needs to be fetched again.
With a split cache, the code and data segments
no longer overlap. Caching
code cannot overwrite data, caching data cannot overwrite code.
The drawback is
that only 32k of data and 32k of code can be cached at once (in
a 64k system),
but usually this provides for more speed than being able to cache
a 64k mix of
both.
To do the mod, you'll need a ZipGSX version
1.02 with either 16k or 64k
cache on it. If you're not sure exactly what board you have, it's
pretty
straightforward to figure things out: open the computer and look
at the Zip.
The board revision is silkscreened on just beneath the processor.
The cache size can be determined from the
DIP switch settings. However, a
simpler guideline is look at the TAG/DATA sockets and count the
number of
chips. If there are only 2 chips, you have either an 8k or a 32k
cache. If
there are 4, then you should have 16k or 64k.
To modify your Zip for the Split Cache,
you'll need a good hobby knife
that can cut the traces without damaging the board underneath too
badly, as
well as two or three small lengths of wire. You will also need
a good
pencil-style soldering iron, desoldering pump or braid, and high
quality rosin
core (NOT acid core) solder. I use Radio Shack's .032 60/40 rosin
core solder.
Kester makes excellent quality solder which is sold at many electronics
supply
shops.
There is a potential of damaging expensive
and delicate hardware. For
example, when cutting a circuit trace be careful not to cut deeply,
lest you
cut a trace in the next layer of the circuit board. If you're not
experienced
with cutting traces or soldering on circuit boards, find an old
board and take
some time to practice.
The actual mod is very simple. Steps 1-3
and 5 are for all boards. Step 4
is for 16k cache boards only. (Note: The picture in FAQs resource
file
R005SPLITC may be helpful for doing these mods.)
1. Locate J6 and J7. They are both blocks of 3 pinholes, which
may or may not
have been soldered-in, near the bottom of the board next to connector
J1, where
the gray cable attaches.
2. Cut the SMALL trace between pins 2 and 3 of both J6 and J7. This
trace is on
the back (solder side) of the board.
3. Solder in a piece of wire between pins 1 and 3, of both J6 and
J7. A wire
that has been bent into a U shape before soldering seems to work
best, both for
ease of installation and aesthetic value.
4. 16k systems ONLY: (See the "16k" insert on the picture in FAQs
resource file
R005SPLITC.) Cut the trace between pins 1 and 2 of J8 on
the top side of the
board. (J8 is below the Cache SRAM sockets) Then, solder
a piece of wire
between pins 2 and 3 of J8.
5. Set the DIP switches appropriately. The DIP switches needing
to be set are
SW1-7 and SW1-8, they control the cache size. SW1-7 should be OFF
for 64k, ON
for 16k. SW1-8 should be ON.
Reversing these changes is fairly easy.
If you decide that the performance
change was detrimental, simply desolder the wires that you installed,
and
solder in wires to replace the traces that were cut.
I found that the split cache sped up my
system notably, especially under
the Finder and other desktop applications. Improvement was much
less noticeable
under text applications. (I haven't checked affect on compiling
speed, yet.)
From: Rubywand
I tried the split-cache mod on my 10MHz/64kB
ZipGSx. Before/after timings
were done for several tasks including Scrolls through Finder windows,
Scrolls
and Find/Replace through Coolwriter (super-res) and Appleworks
(plain text)
documents, and Platinum Paint fills.
Timing differences were very small-- usually
within the error normally
experienced when clicking a stopwatch for repetitions of identical
events.
Where a difference was observable, it favored the unified 64kB
cache.
Evidently, at least on a 64kB board, the
ZipGS does a fairly good job of
managing the unified cache. Possibly, the mod comes out ahead in
some tasks not
sampled; or, it may work better on 16kB boards.
013- I have a 7MHz ZipGS. How fast can the board be pushed without
getting new SRAMs or a new CPU? What
parts do I need?
You may be able to get it to run at up
to 10MHz by just replacing the
oscillator with a faster one for less than two dollars!
I have a Zip GS that came as a 7/32 and
was used at 7MHz for a long time.
The board came with a socketed oscillator, so one day I swapped
out the 28MHz
oscillator for a 36MHz one. The computer booted up at 9MHz. When
the 36MHz osc
was replaced with a 40MHz osc, the Zip ran at an amazing 10MHz!
Your mileage may vary, though. The GS that
this upgraded Zip resides in
has a high output power supply. Still, considering these oscillators
cost $1.39
each, it is worth getting three or four and trying an oscillator
swap alone
first. If a faster oscillator alone won't do the trick, then a
faster CPU
and/or faster cache chips may be necessary.
Good Luck!
014- What Oscillator freq corresponds to what TWGS/ZipGS
operating speed?
For TWGS and ZipGS, the crystal oscillators
runs at 4 times the speed of
the 65816. Below is a chart showing osc and corresponding TWGS
or ZipGS speed.
Osc Frequency MHz
TWGS/ZipGS Speed MHz
32
8
33.3333
8.3333
36
9
40
10
42
10.5
46
11.5
48
12
50
12.5
55
13.75
60
15
My understanding is that, if you over-clock
a CPU. It just won't function.
You can't damage it. As the disclaimer said, do it at your own
risk. I have
tried to run my TWGS at 20 MHz, system won't boot at all. No damage.
015- How do I experiment with different oscillator frequencies?
Most of the following is from a piece on
ZipGS upgrading by Long. It is
also a useful guide for TWGS owners.
The Zip can use three types of crystals
including the common 4-pin full
TTL crystal oscillator, 4-pin 1/2 TTL crystal oscillator (also
used on TWGS)
and 2-pin crystal (little metal canister about 1/4 the size of
1/2 TTL). To be
able to use a 2-pin crystal, your Zip must have a resistor at R1
and capacitors
at C13 and C14. I've found these three parts to be missing
from current Zips.
No big loss since 2-pin crystals are less common and are only available
up to a
certain frequency.
For experimenting with different frequencies
it makes it easier if you
install a socket for the crystal oscillator. It's also a
good idea to secure
the module with one of those zip tie bands. Only 6 of the 14 pins
are used
(picture A). The ground (GND) pins 1, 4 and 7 are connected together.
The
power pins 11 and 14 are connected together. Full TTL crystal
oscillators use
pins 1, 7, 8 and 14 (refer to picture B). 1/2 TTL crystal
oscillators use the
bottom four pins (4, 7, 8 and 14; picture C). Make sure it's
oriented
correctly with the corner (usually with a dot printed next to it)
at about 11
o'clock.
*WARNING* The crystal oscillator will be damaged if
installed
incorrectly.
_______
GND 1 o
o 14 POWER 1 |o
\ 14
NC
x x NC
| |
NC
x x NC
| FULL |
______
GND 4 o
o 11 POWER | TTL
| 4 |o
\ 14
NC
x x NC
| |
| 1/2 |
NC
x x NC
| |
| TTL |
GND 7 o
o 8 CLOCK 7 \______/
8 7 \_____/ 8
(A) (B) (C)
x - no connection (NC)
016- How do I modify my ZipGS to accept the new "skinny" RAM chips?
With a little modification you can make
a Zip with wide sockets accept
both the wide (600 mil) and the newer 300 mil skinny 32k x 8 Static
RAMs
(SRAMs). Ground yourself then carefully pry out the static rams.
Look at the
socket and you will notice two or three horizontal bars holding
both sides of
the socket together (Picture D). Carefully snip those out
(wire cutters work
well for snipping plastic). This will expose a column of holes.
Now, solder in
half of a socket.
Refer to Picture E below. Plug your skinny
SRAMs into the left and center
columns making sure the notch on the static ram is facing up--
i.e. toward top
edge of board. (Applying power with a chip incorrectly socketed
could damage
the chip.)
CUT
___ ___________
Skinny RAMs plug in here
|
| | |
notched end facing up.
____ ____ _ _
_
|o __V__ o| |o| |o| |o|
|o| o |o| |o| |o| |o|
|o| o |o| |o| |o| |o|
|o| o |o| |o| |o| |o|
|o| o |o| |o| |o| |o|
|o| o |o| |o| |o| |o|
|o|__o__|o| |o| |o| |o|
|o _____ o| |o| |o| |o|
|o| o |o| |o| |o| |o|
|o| o |o| |o| |o| |o|
|o| o |o| |o| |o| |o|
|o| o |o| |o| |o| |o|
|o|__o__|o| |o| |o| |o|
|o _____ o| |o| |o| |o|
(D)
(E)
017- Is it really necessary to increase board
voltage
to do a TWGS/ZipGS speedup?
With the new 14 MHz parts, you should not
need to mess with the voltage at
all. It _may_ be necessary to increase voltage at 15-16MHz and
will likely be
necessary at higher frequencies (e.g. 20MHz).
018- If I do a TWGS/ZipGS speedup mod, what
kind of performance
increase can I expect?
This is just to give you a rough estimate of how much faster you
might be able
to achieve...
BenchMark v5.0 results:
CPU Stock
TWGS TWGS TWGS ZipGS ZipGS
ZipGS
Version ROM 01 1.8s
1.8s 1.8s 1.0.2 1.0.2 1.0.2
Cache/Spd
32k/15 32k/15 32k/15 64k/?? 64k/?? 64k/??
Clock Spd 2.8 15
13.75 12.5 16
15 14
=======
====== ====== ====== ====== ====== ======
Sieve 410.00 99.00
108.00 117.00 98.00 99.00 110.00
String 1151.20 270.00 292.00 303.67
259.00 262.00 282.00
Float 1 472.00 92.33
87.00 111.33 123.00 128.00 135.00
Float 2 1535.00 317.00 394.00 381.67
395.00 415.00 432.00
Fibinacci 2006.00 605.00 634.00 645.33
507.00 523.00 548.00
Integer 1553.40 307.00 330.00 346.67
420.00 431.00 443.00
Dhrystone 236 1136
1063 1000 NA
NA NA
*
1351 1183
1282 NA NA
* Dhrystone v1.1 re-compiled under ORCA/C v2.0.1
System Software 5.0 QuickDraw II improvement test:
Stock //gs: 5648
ticks
TWGS 15 MHz: 1332 ticks
(over 4x faster than stock)
If you look at the numbers, a 12 MHz or faster TWGS/Zip will make
everything
just about 4x faster than a stock //gs.
019- How can I modify my ZipGS for more cache and more speed?
The process described below is very simple.
It aims for a speed of 12.5MHz
(or better) with 64k cache.
First, you will need one of the new Western
Design Center 14MHz 65C816's.
Alltech Electronics stocks the WDC65C816-14MHz for $20. Students,
teachers, and
professors can order the IC in single quantities directly from
WDC for around
$7.
Adaptors: Nearly all of the newer, faster
32k x 8 SRAMs are in skinny
300-mil packages. If you would rather not modify your ZipGS for
the skinny
SRAMs, Digi-Key stocks 300-mil to 600-mil adapter sockets for about
$7 each.
The ones you want are part number A502-ND. You can plug a
28 pin SRAM into the
300-mil adapter socket and the adapter in turn plugs into the 600-mil
socket on
the Zip. (If you have some spare sockets lying around, you can
build your own
cheap, but that's another story.)
2-4 32k x 8 SRAM chips: There are many
sources for 32k x 8 SRAMs and
several types that will work. I got mine (HM62832-15, $5 each)
from JDR
Microdevices. You'll want 15ns in the Tag RAM sockets. Up to around
12.5MHz,
you want 70ns or faster Data RAM. If current cache size is 64k,
your old TAG
RAM chips will, usually, work as Data RAM and can be transferred
to the Data
sockets. Otherwise, go ahead and get two 25ns-35ns 32k x 8 SRAM
chips for the
Data RAM.
Data RAM should always be slower than Tag
RAM. Barry Rees posted his
experiences on this matter (that Data should be significantly slower
than Tag)
and I found that the original Tag chips were fast enough.
A "full size" oscillator module: Digi-Key,
JDR, Mouser, ... have these.
Divide oscillator speed by four to get Zip speed. JDR has the OSC50.0
(50MHz
oscillator), which will make a 12.5MHz Zip. The oscillators are
cheap enough to
get two or three for experimenting with higher speeds.
So, you just plug your Tag and Data RAM
chips into the Digi-Key adapters
and plug the adapters into the Tag and Data sockets of the Zip.
Then, you
install the new 65C816 and oscillator and make sure DIP switch
1-7 and 1-8 are
both set OFF (for 64k cache). That's it, done completely without
soldering.
ZipGS boards vary. On some you may be able
to go above 12.5MHz by just
plugging in a faster oscillator. On others, you may have to choose
between
getting faster Data RAM or settling for a lower speed. The new
65C816 is rated
for 16MHz and many users have gone to 14MHz and above. For speeds
above
12.5MHz, the usual recommendation is to get Data RAM rated at 35ns
or better.
For a step-by-step guide, download my ZipUpgrade.SHK
HyperCard stack at
ftp://ground.ecn.uiowa.edu/apple2/apple16/Hypermedia/Hypercard/
.
020- Do I need new GALs to speed up my TransWarpGS?
Not any more. The new 14MHz 65C816's available
from WDC make it
unnecessary to swap in new GAL chips to go to higher speeds.
021- I have an 8kB TransWarpGS. How does a cache upgrade compare
with a speed upgrade?
John Link charted some comparisons in 1991
involving nine setups: no-TWGS,
and 7, 8, 9, 10mHz boards before and after the 8kB-to-32kB cache
upgrade. He
used three benchmarks:
1. time to calculate page breaks in a 218-page Appleworks document
2. time to scroll through a 39-page Awks-GS document
3. time to compile 4800 lines of MD-BASIC source code
For a 7mHz 8kB TWGS, the speed gain for the 32kB cache upgrade is
roughly 33%
to nearly x2.5 plain GS speed.
For a 10mHz 8kB TWGS, the speed gain for the 32kB cache upgrade
is roughly 33%
to about x3.25 plain GS speed.
His charts shows that a 7mHz TWGS with
the 32kB cache performs slightly
better than a 10mHz TWGS with 8kB cache on tests 1 and 3; it is
a bit slower on
test 2.
022- How can I upgrade my TWGS to 32k cache?
SHH Systeme ( http://users.ids.net/~kerwood/shh.html
), a German company,
sells the cache upgrade piggyback board in various states of 'do-it-yourself'
readiness. The ready-to-go version is $69 (+ $14 S&H). It includes
three 32K
cache RAMs (62256-15 or equivalent) and can support speed upgrades
to 14MHz or
better.
SHH does not automatically include the
firmware ROM. If your firmware
version is not v1.7 or v1.8, you will also need to order the v1.8
EPROM which
SHH sells for $12.
023- How can I upgrade TWGS speed?
The process is very similar to that described
earlier for the ZipGS. That
is, you swap in a new 14MHz 65C816, a higher speed oscillator module,
and,
possibly, faster 32k x 8 SRAM chips.
As with ZipGS, TransWarpGS speed = Osc
Speed divided by 4. One difference
is that the TransWarpGS oscillator module is of the "half-size"
kind. Another
is that, if RAM is upgraded, the usual practice is for all three
to have the
same speed rating. If you do the SHH cache upgrade, there should
be no need to
worry about replacing SRAM.
According to a 1992 Appleworks Forum article
by John Link, you can get to
12.5MHz with the new 65C816, a 50MHz oscillator, and 35ns SRAM.
Higher speeds
would require faster SRAM. (The article mentions that increasing
power supply
voltage to 5.5V allowed operation at 13.75MHz with a 55MHz oscillator
and 35ns
SRAM; but, that malfunctions began to occur after 2 hours.)
TransWarpGS boards vary just as do ZipGS
boards. Some can be pushed to
higher speeds than others. If you decide to do a speed upgrade,
get two or
three oscillators to allow for some experimentation.
For a step-by-step guide, download Scott
G's TWGSupgrade.SHK. HyperCard
stack at ...
ftp://ground.ecn.uiowa.edu/apple2/apple16/Hypermedia/Hypercard/
.
024- What kind of RAMs do I need for a TWGS or ZipGS speedup?
You need fast 32k x 8 Static RAM in a 28-pin
Dip package. If your RAM
sockets are "skinny" (about as fat as a typical 74xx TTL IC), you
want a
300-mil wide package. Otherwise, you will need a 600-mil wide IC
or a socket
adaptor for 300-mil (or do the socket mods described earlier in
this FAQ).
Fast 600-mil package 32k x 8 SRAMs are
fairly rare. However, the IDT71256
is supposed to be available at good speeds (25ns-40ns) in a 600-mil
version
from Integrated Device Technology.
The selection of 300-mil 32k x 8 SRAMs
is much larger: Cypress's CY7C199,
Hitachi's HM62256, ... .
025- How can I tell the firmware version of my TWGS?
With the IIGS turned on, press CONTROL-Apple-ESCAPE
And go to the
Transwarp CDA The ROM version will be displayed on the screen.
026- Do I need I need the 2B GAL for my Transwarp-GS to use a
SCSI interface? If I do, where can
I get one?
The TWGS-2B GAL was a DMA fix Applied Engineering
issued for the board. It
is an absolute requirement for Transwarp to work at all with at
least some
RamFAST SCSI boards (e.g. the revision C boards).
With Applied Engineering long since out
of business and the GAL virtually
impossible to duplicate by convential means, that leaves no good
source for
replacement GALs. I found it much more affordable (and less hassle)
to just
purchase a used TransWarp GS board with the 2B GAL to replace your
old one.
From: Supertimer
RamFAST revision D does not require the
2B GAL. The Apple High Speed SCSI
card works with all TransWarps GS units.
027- When I change my ZipGS's Speed, Misc, and Slot settings
via
the Zip CDA, they are always lost after
turning OFF the GS.
What's wrong? Do I need a new BatRAM
battery?
No. The reason the settings are forgotten
is that they are not saved in
BatRAM or on-disk. ZipGS settings made via the Zip CDA or via the
Zip Control
Panel are only in effect for the current session of computing.
028- What do the check-marks mean next to settings
in the ZipGS
CDA? Are they original factory settings
or what?
More like "or what". The check-marks indicate
the settings of the DIP
switches on your ZipGS board.
029- After installing my ZipGS along with the
ZipGS CDA and other
software I've noticed that my ZipGS
settings never seem to
match the ones I originally set via
the on-board DIP
switches!?
There are two likely explanations. One
is that your interpretation of the
settings is confused due to the rather poor explanations provided
in the Zip
on-disk HyperStudio 'manual'. It does not help that names/descriptions
of the
settings are not quite the same in the 'manual' and in the CDA
or NDA.
For info on setting your on-board DIP switches, see question 001.
Another possibility is that when you installed
the ZipGS software, you
installed ZipInit in your SYSTEM/SYSTEM.SETUP folder. If you did,
then whatever
settings ZipInit is set up for will be the settings for your ZipGS
after
booting. That is, ZipInit will over-ride your DIP switch settings.
ZipInit is intended for use on diskettes
which, when booted, will set up
the ZipGS in some special way to match the software on the diskette.
For
example, you might want to turn OFF the ZipGS or reduce its speed
when booting
an arcade games diskette.
The cure for unwanted influence from ZipInit
is to delete it from your
SYSTEM/SYSTEM.SETUP folder.
030- I have a ZipGS. Usually, it runs like
a champ; but, sometimes
when I power-ON my GS, I get an all-white
screen and the computer
just 'hangs'. What's going on?
It may be that your ZipGS card is not making
good contact in its Slot
socket. This is a fairly nasty problem which has led users to pursue
a number
of false cures.
With power OFF, pull your ZipGS board and
inspect the bottom-of-card
connectors. What you will, most likely, notice is that the connector
traces end
approximately 1/8 inch or so from the bottom of the card.
Unfortunately, the GS Slot sockets make
contact rather near the bottom of
cards plugged into them-- roughly 1/8 inch or so from the bottom.
The reason
your GS sometimes hangs is that, sometimes, the ZipGS card is not
making good
contact with all Slot connectors.
One 'cure' is to make sure the ZipGS card's
contacts are clean and that
the card is thoroughly plugged in-- i.e. well lined-up with Slot
contacts and
inserted as far as it will go into the Slot socket.
A mildly tricky additional step is to use
a small jeweller's screwdriver
to reach into the Slot socket and _carefully_ twist/pull/bend-out
each contact
very slightly (naturally, with power OFF). You do not want any
contact to
normally touch a contact across from it.
Whatever, if your GS starts okay and does
not exhibit the same kind of
hanging in the future, you know that the ZipGS card is well socketed.
A more permanent, reliable cure is one
_not_ recommended for someone
without experience working on circuit boards: You find a better
Slot connector
socket-- one with gold contacts which touch plugged-in cards higher
up and with
circuit board connections which will fit into the original holes--
and replace
the connector. This is a _very_ tricky replacement which requires
careful
de-soldering of the original Slot socket, cleaning of contact holes,
and
soldering-on the new socket-- all without burning the circuit board
or slicing
traces on either side. Actually, slicing traces is okay, IF you
are prepared to
repair the damage. (Yes; I did this replacement on our GS. It works;
but, If I
had known what a hassle it would be, I probably would never have
done it!)
031- Ever since my accelerator speed upgrade
it seems like my GS is
always experiencing random system crashes.
What's the problem
and how can I fix it?
When a GS equipped with an accelerator
experiences frequent crashes
into the monitor after a speed upgrade, the usual explanations
are ...
1. the accelerator is over-clocked for the microprocessor or RAM;
2. there are serious noise spikes on the Slot power lines.
If you are 'pushing' your current RAM or
using an old 65C816, you can
upgrade to faster chips or swap in a slower oscillator.
Often, the problem will be noise spikes
related to increased current load
and/or increased sensitivity to noise related to faster clocking.
See the POWER
FAQs for Power Supply and motherboard mods which should help.
032- I added a new accelerator board to my
Apple and now my
system is constantly bombing. What's
the problem and how
can I fix it?
Most likely, the accelerator board's current
load has led to increased
noise on the +5V bus. See the POWER
FAQs for Power Supply and
motherboard mods which should help.
